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  1. Is there a free eagle sch viewer to view the .brd and .sch files?

    Oct 26, 2015 · Can anyone recommend free software to view the .brd and .sch files? Is there a free viewer for Eagle ? I have what should be a schematic file from a vendor, its suffix is .sch. I …

  2. [SOLVED] - How to measure distance in EAGLE? - Forum for …

    Jul 16, 2009 · How to measure in EAGLE? Somebody knows how to measure a distance between two points in EAGLE? Whether there is in it a ruler and snap, how in P-CAD?

  3. [SOLVED] - Eagle ULP script to convert kicad to eagle

    Jun 7, 2007 · Hi John, Obviously this thread is really old, but I wanted to add this here to help out any other people searching for this. I've put together an improved Eagle to KiCAD schematic …

  4. How do you make a Non Plated Through Hole for Mounting - Altium

    Mar 1, 2022 · As the title asks how do you make a non plated through hole in altium? What I am trying to do is have a hole in between two seperate planes which are set to two different net …

  5. help me to kill the process (cadence) | Forum for Electronics

    Oct 28, 2005 · cadence + kill can anyone help me..i cannot edit my design (cadence) after my pc is hang,, after restart my pc i cannot edit my design,,anyone can help me what is the …

  6. What is the use of Data strobe | Forum for Electronics

    May 17, 2008 · Dear All, Please explain me what is the use of Data strobe in DDRAM. Already there is a read and write signal is there for transfering data right? Then what for Data strobe? …

  7. [SOLVED] - How do we set max fanout for clock nets

    Aug 11, 2020 · Hello everyone, Could you show me how to set max fanout for clock nets in cadence innovus 18.1? Thanks so much!

  8. What is output voltage of fullwave rectifier if input is 230v AC?

    Apr 28, 2011 · hi, i am designing a super led night lamp using high power leds. ... i have attached that ckt ... in that ckt i need to build a fullwave rectifier,so made it using doides IN4007 input …

  9. Gotchas in SystemVerilog RTL Design | Forum for Electronics

    Sep 12, 2025 · As more and more RTL designs are written in SystemVerilog rather than Verilog, there are unexpected gotchas that only show up late in the flow — during synthesis, …

  10. unmatched nets in the layout | Forum for Electronics

    Feb 14, 2018 · its own. You could investigate these conjectures in the PDK structure if you didn't have the more useful task of fixing your schedule-bog by way of achieving design consistency. …