Design-Reuse1mon
DDR3 PHY
IP is a general-purpose IP that provides connectivity between a DDR3 memory Controller (MC) and the DDR3 memory devices compliant with JESD79-3 specification. The DDR3 PHY IP provides the Industry ...
Design-Reuse3y
DDR4 / DDR3/ DDR3L / LPDDR4 Memory Controller IP optimized for low latency
The DDR IP is compliant with the latest JEDEC standards and is silicon proven. This memory controller supports DDR4, DDR3, DDR3L, LPDDR4 SDRAM. This memory controller is a high-speed interface used ...