EDN

New development environment provides simplified SystemC debug

SAN FRANCISCO — Summit Design Inc. has introduced an integrated development environment (IDE) for SystemC-based analysis and debug. The tool, Vista 1.1, is an improved version of the Vista IDE that ...
Electronic Design

IDE Lays SystemC Designs Bare For Easier Debugging

Sometimes design abstraction is a help, and sometimes it's a hindrance. Verification of system-on-a-chip designs with SystemC has a demonstrated ability to significantly speed up simulation runs.
Design-Reuse

Aldec Releases Integrated SystemC Debugging Environment with Assertion-Based Verification

Henderson, Nevada - December 27, 2004-- Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, today announced the release of Riviera 2004.12. The new ...
Design-Reuse

Forte Design Systems And Summit Design Join Forces To Deliver An Enhanced SystemC to RTL Design, Synthesis, And Verification Environment

Integration of Cynthesizer and Vista SystemC IDE Greatly Improves Design Team Productivity and Workflow Management San Jose and Los Altos, Calif - December 6, 2005 - Forte Design Systems, the leading ...
EDN

Aldec blends SystemC, HDL debugging

SANTA CRUZ, Calif. — Expanding its capabilities for mixed-language simulation of ASICs and FPGAs, Aldec Corp. this week (Dec. 27) announced the release of Riviera 2004.12. New features include ...
uni

SystemC to Timed Automata Transformation Engine (STATE)

STATE takes a SystemC design as input and transforms it into a corresponding UPPAAL timed automata model. The transformation is based on a formal semantics defined for SystemC in ...