Traditionally static timing analysis (STA) is used to verify if a CMOS digital design can meet the target speed at various process and interconnect corners. In practice, the worst-case slow or ...

About five years ago if you listened to the marketing messages in the EDA industry, you would have thought it would be impossible to produce chips without statistical static timing analysis (SSTA).

Since DAC 2005, there has been extensive discussion about using Statistical Static Timing Analysis (SSTA) to verify current and future generations of designs manufactured at 90 nm or below. Given the ...

Statistical static timing analysis (SSTA) is gaining in popularity these days, particularly as 65-nm processes move toward maturity and designers become increasingly concerned about fab yields. SSTA ...