Design-Reuse

Designing Around an Encrypted Netlist: Is The Pain Worth the Gain?

Oftentimes, in order to save on the cost of IP, a company will select an encrypted netlist as the deliverable instead of the RTL source code. This is especially common among companies looking to ...
EDN

KaiSemi claims automatic FPGA-to-ASIC conversion

Using a variety of processes from 90 to 500 nm, fablesssemiconductor vendor KaiSemi Ltd recently unveiled automatedconversion, a process to convert most currentFPGA designs to drop-in ASIC ...
EDN

FPGA-ASIC conversion: Is automatic an option?

FPGA-to-ASIC conversion doesn't get a lot of press. Formany teams who design-in an FPGA, conversion to a cost- and power-saving ASICis at best an afterthought. Let's ship this thing, and then we can ...
Design-Reuse

Domain Technologies announces Synthesizable MRAM8051 Microcontroller Netlist Library for Actel FPGAs Including Royalty-Free License for use in Tekmos Merged ASICs

Plano, Texas , October 12, 2006 - Domain Technologies announces the availability of the industry's first, royalty-free, synthesizable MCS8051 code-compatible microcontroller netlist library and ...
New Electronics

FPGA Retargeting: The Why, What and How

The practice of retargeting an existing design from one FPGA technology to another has received a lot of attention. Why should design teams consider this strategy? By Sreedhar Mallela. Recent supply ...
Semiconductor Engineering

FPGA Equivalence Checking For A Nuclear Safety Controller

Every chip development team wants to find and fix all the bugs they possibly can in pre-silicon verification. Turning a chip to fix issues found in the bring-up lab incurs high costs and product ...
Semiconductor Engineering

Why Your FPGA Synthesis Flow Requires Verification

When you think about it, logic synthesis is a vital but rather intimidating part of modern chip design. This process takes a high-level description of intended functionality, written in an RTL ...
Electronics Weekly

In FPGA design timing is everything, says Synopsys

When your FPGA design fails to meet timing performance objectives, the cause may not be obvious. The solution lies not only in the FPGA implementation tools’ talent in optimising the design to meet ...
Electronics Weekly

OneSpin spins equivalence checker for FPGA users

Formal verification tool maker OneSpin Solutions has made its 360 EC (equivalence checker) available to the FPGA market. The pushbutton EC FGPA tool helps FPGA designers ensure that RTL (register ...
Electronic Design

Equivalence Checker For FPGAs Unearths Synthesis Errors

FPGAs, popular as they are these days for prototyping and/or production runs, come with their own little quirks. One of those is the nagging tendency for functional errors to appear in synthesis and ...
New Electronics

Addressing safety critical FPGA designs

Field-programmable gate arrays (FPGAs) are the dominant hardware platform in many safety-critical, low-volume applications, including aerospace and nuclear power plants (NPPs). Modern FPGA devices ...