The EPC8010 power transistor, sold in die form, measures 1.75 mm 2 with 100 VDS. Optimized for high speed switching, the device has a maximum R DS(on) of 160 mΩ and input gate charge in the hundreds ...

(Application Note) Here is a new Application Note from Nanosurf on conductive AFM (C-AFM) measurements on a polished IC surface with multiple transistor contacts. Chemical-mechanical polishing (CMP) ...

(Nanowerk Spotlight) For over fifty years, the relentless miniaturization of silicon transistors has upheld Moore’s Law, delivering exponential leaps in computing power. However, this development ...

Traditional CMOS chips are fabricated by applying and then etching repeated layers of different materials, applied to a wafer of ultra-pure silicon. The bottom-most layer, also known as the front end ...

For decades, chipmakers have squeezed more computing power out of silicon by shrinking transistors, but that strategy is ...

Many DSP chips, microprocessors, FPGAs, and ASICs require multiple power supplies that must deliver different voltages in a specific start-up sequence. Out-of-sequence voltages can cause excessive ...

Researchers have found a low-cost way for backscatter radios to support high-throughput communication and 5G-speed Gb/sec data transfer using only a single transistor when previously it required ...

Silicon transistors and the brain don’t mix. At least not optimally. As scientists and companies are increasingly exploring ways to interface your brain with computers, fashioning new hardware that ...