EDN

Building an FPGA FIFO without using logic resources

Today, FPGA designers are using these flexible devices to perform everything from simple glue logic tasks to implementing complicated system on a chip (SoC) functions. The efficiency and ease of ...
EDN

RTL coding architecture affects power estimation & analysis

A well thought out design flow for SoCs ensures that the resulting device meets the requirement of low power dissipation. To meet these goals at the device level, individual modules (or components of ...
Electronics Weekly

SPI FIFO can configure serial clock signal

Digital Core Design, the Poland-based IP core design house, has developed the DSPI_FIFO, a fully configurable SPI master/slave device, which allows the SoC designer to configure polarity and phase of ...
Electronics Weekly

IDT expands dual-port, FIFO families

Supporting the evolving bandwidth needs of the next-generation wireless and networking infrastructure, IDT has added devices to its multi-port and first-in/first-out (FIFO) families. The 36Mbit ...
Design-Reuse

Making SPI-4.2 Implementations More Efficient: Part 1

The SPI-4.2 interface has quickly achieved the industry-wide recognition and is highly accepted as standard high-speed interface in the networking chip space. However, creating an efficient SPI-4.2 ...